208 Coordinated Science Laboratory
1308 West Main Street
Urbana, IL 61801
Rakesh Kumar is an Associate Professor in the Electrical and Computer Engineering Department at the University of Illinois at Urbana Champaign. His current research interests are in computer architecture, low power, trustworthy and error resilient computer systems, and approximate computing. His research and teaching have been recognized through several best paper awards and best paper award nominations (ASPLOS, HPCA, CASES, SELSE, IEEE CAL, SRC TECHCON), Ronald W Pratt Faculty Outstanding Teaching Award, Engineering Council Award for Excellence in Advising, ARO Young Investigator Award, Arnold O Beckman Research Award, FAA Creative Research Award, and UCSD CSE Best Dissertation Award. He also previously served as a Co-Founder and Chief Architect at Hyperion Core, Inc, a microprocessor startup aimed at bringing polymorphous grid processor technology to the market. Rakesh has a BS from IIT Kharagpur and a PhD from University of California at San Diego.
Low Power Computing (HPCA18, ISCA17, ASPLOS17, HPCA17, ISLPED16, ISCA16, HPCA15, ISLPED14, HPCA12, MICRO09..)
Approximate Computing (DAC16, ICCD14, ICCAD13, ICCAD12, DSN12, DAC12, DAC10, CASES11, DSN10, DATE10, HPCA10, ASPDAC10..)
Memory Systems (HPCA17, ISCA16, HPCA16, SC14, SC13, HPCA13..)
Security, Privacy, and Trust (MICRO17)
A Case for Packageless Processors, HPCA, 2018, (PDF).
Software-based Gate-level Information Flow Security for IoT Systems, MICRO, 2017, (PDF).
Bespoke Processors for Applications with Ultra-low Area and Power Constraints, ISCA, 2017, (PDF).
Determining Application-specific Peak Power and Energy Requirements for Ultra-low-power Processors, ASPLOS, 2017, (PDF). (Best Paper Award).
Enabling Effective Module-oblivious Power Gating for Embedded Processors, HPCA, 2017, (PDF)
Understanding and Optimizing Power Consumption in Memory Networks, HPCA, 2017, (PDF)
Bit Serializing a Microprocessor for Ultra-Low-Power, ISLPED, 2016, (PDF)
Rescuing Uncorrectable Fault Patterns in On-Chip Memories Through Error Pattern Transformation, ISCA, 2016, (PDF)
(an earlier version selected as a Best Paper at SRC TECHCON 2015).
Exploiting Dynamic Timing Slack for Energy Efficiency in Ultra-Low-Power Embedded Systems, ISCA, 2016, (PDF)
Approximate Bitcoin Mining, DAC, 2016, (PDF)
Parity Helix: Efficient Protection for Single-Dimensional Faults in
Multi-dimensional Memory Systems, HPCA 2016, (PDF).
Correction Prediction: Reducing Error Correction Latency for On-Chip Memories, HPCA 2015, (PDF).
(an earlier version selected as a Best Paper at SRC TECHCON 2014).
ECC Parity: A Technique for Efficient Memory Error Resilience for Multi-Channel Memory Systems, SC 2014, (PDF).
Software Canaries: Software-based Path Delay Fault Testing for Variation-aware Energy-efficient Design, ISLPED 2014, (PDF).
Markov Chain Algorithms: A Template for Building Future Robust Low Power Systems, Asilomar 2013, (PDF).
Low Power, Low Storage Overhead Chipkill Correct via Multi-Line Error Correction (Multi-ECC), SC 2013, (PDF)
(an earlier version selected as the Best of IEEE Computer Architecture Letters 2013).
On Reconfiguration-Oriented Approximate Adder Design and Its Application,ICCAD 2013, (PDF).
An Algorithmic Approach to Error Localization and Partial Recomputation for Low-Overhead Fault Tolerance on Parallel Systems, DSN 2013, (PDF).
Adaptive Reliability Chipkill Correct (ARCC), HPCA 2013, (PDF).
On Logic Synthesis for Timing Speculation, ICCAD 2012, (PDF).
Algorithmic Approaches to Low Overhead Fault Detection for Sparse Linear Algebra, DSN 2012, (PDF)
(an earlier version selected as a Best Paper at SRC TECHCON 2011).
Compiling for Energy Efficiency on Timing Speculative Processors, DAC 2012, (PDF).
On Software Design for Stochastic Processors, DAC 2012, (PDF). (invited)
Power-Balanced Pipelines, HPCA 2012, (PDF).
(Nominated for Best Paper Award).
Architecting Processors to Allow Voltage/Reliability Tradeoffs. CASES 2011. (PDF). (Best Paper Award).
On the Efficacy of NBTI Mitigation Techniques, DATE 2011, (PDF).
MOPED: Orchestrating Interprocess Message Data on CMPs, HPCA 2011, (PDF).
A Numerical Optimization-based Methodology for Application Robustification: Transforming Applications for Error Tolerance, DSN 2010, (PDF).
Recovery-driven Design: A Methodology for Power Minimization for Error Tolerant Processor Modules, DAC 2010, (PDF).
Stochastic Computation, DAC 2010, (PDF) (invited).
Scalable Stochastic Processors", DATE 2010, (PDF).
Designing Processors from the Ground Up to Allow Voltage/Reliability Tradeoffs, HPCA 2010, (PDF).
Slack Redistribution for Graceful Degradation Under Voltage Overscaling. ASPDAC 2010, (PDF).
Reducing Peak Power with a Table-Driven Adaptive Processor Core, MICRO 2009, (PDF).
Jose Rodrigo Sanchez Vicarte
John Sartori (First Employment: Assistant Professor, EE Department, University of Minnesota)
Joseph Sloan (First Employment: Assistant Professor, EE Department, University of Texas at Dallas)
Henry Duwe (First Employment: Assistant Professor, EE Department, Iowa State)
Xun Jian (First Employment: Assistant Professor, CS Department, Virginia Tech)
Packageless Prcessors [Semiconductor Engineering]
Bespoke Processors [IEEE Spectrum][Semiconductor Engineering][Hackaday][CircleID]
Approximate Bitcoin Mining [ZDNet][Slashdot][EE Times][Hacker News][Security Affairs][Coin Report][CryptoCoinNews][Coin Telegraph][Brave New Coin][NewsBTC][More]
Stochastic computing, Approximate computing, Error tolerant computing [BBC]][HPCWire][IEEE Spectrum][Engineering&Technology][Slashdot]
Hardware Support for Novel Business Models for Many-cores [HPCWire]
[New Gazette] [ACMNews]
[Dr Dobb's Journal]
Addressing Programmability and Power Challenges of Many-core Computing [News-Gazette][ZDNet][ACMNews] [More]
Heterogeneous Computing [HPCWire]
DARPA, DOE, NSF, SRC, NSA, ARO, Intel, AMD, Oracle, Cisco